Due to manufacturing limitations in Integrated Circuits (ICs), elements vary in properties from each other even if such circuits are intended to be exactly the same. Such variations can be systematic and/or random. Mismatches between different elements often causes non-idealities in the circuits.
Conventional approaches to mitigate the problem of mismatch among different elements in electronic circuits implement various forms of calibration. Calibration is often performed against a fixed reference element. The more complexity in such calibration systems, the more chip area needed.
It would be desirable to implement a system that reduces the size and cost of calibrating an electronic component manufactured on an integrated circuit (IC).